For an increase in frequency, it is likely that a logic circuit operating at a high-frequency clock, such as a central processing unit (CPU) core, operates at an operation clock that is asynchronous to those of different logic circuits. CPU clocks and bus clocks are asynchronous to each other by inserting an asynchronous bus bridge at the interface between a CPU and an on-chip bus, and thus the operation frequency of the CPU is accelerated.
In addition, with respect to some circuits in the field of in-vehicle devices for which high reliability is needed, since the circuits are redundant by being duplicated by Dual-Core Lock-Step (DCLS), it is possible to secure safety by using a system configuration in which failure is detected during a system operation and the system is safely stopped. If a circuit of a CPU or the like is duplicated by using, for example, a DCLS configuration, the output signals of the duplicated CPUs are compared sequentially. Therefore, in a case where a temporary or permanent failure occurs on one CPU, it is possible to promptly detect the occurrence of abnormality. However, only abnormality is detected in the comparison by duplicated ones, and processes such as backup or recovery are performed separately. The safety needed in the in-vehicle devices is standardized by using an automotive safety integrity level (ASIL) or the like, and a duplication technique of a CPU or the like is used for satisfying the safety.